Rajesh Udenia
Senior Principal Design Engineer
- Role
- Senior Principal Design Engineer at Synopsys Inc
- Location
- Walnut Creek, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Rajesh Udenia
Working in the field of IP/Subsystem digital design from past 20+ years targeted to SoC…
Experience
Senior Principal Design Engineer
Oct 2010 — Present
Digital IP Design, In house and 3rd party IP project management,
Education
Indian Jobs and Careers
B.E.
1992 — 1996
Birla Institute of Technology and Science, Pilani
M.E.
1998 — 1999
Skills
- Asic
- Ethernet
- Systemverilog
- Verilog
- Storage Area Networks
- Fpga
- Embedded Systems
- C
- Modelsim
- Sdh/Sonet
- Testing
- Sdh
- Soc
- Synplify Pro
- Field-Programmable Gate Arrays (Fpga)
- Rtl Design
- Vlsi
- Vhdl/Verilog
- Synchronous Digital Hierarchy (Sdh)
- Application-Specific Integrated Circuits (Asic)
- Quartus
- Debugging
- Xilinx
- Pcb Design
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