Rajesh Surapaneni

About Rajesh Surapaneni

3 Patent Applications and 4 Distinguished Invention Awards (Trade secrets) for outstanding IP contributions• Multiple ATTD and LTD Department/Organizational Awards.• Extensive collaboration with external customers, academic and research institutions, as well as design, simulation and reliability teams to develop integrated, data-driven solutions for advanced packaging.• Led a team of engineers to monitor and analyze the impact of parametric charts, health reports and audits from various modules on key yield indicators across multiple backend modules, layers, technology nodes and products to meet engineering specifications across HVMs.• Led a focus team at managerial level to monitor Fault Detection & Classification (FDC) repositories,ensuring tool matching and process control across HVM tools.• Collaborated with various vendors to identify and select tools, qualifying multiple first-of-a-kind tools by meticulously defining specifications and requirements ensuring seamless integration of new process flows.•Presented a paper at ECTC (2022) and authored more than 100 technical Change Control internal white papers focusing on yield improvement and defect reduction.• Patent Application: Rajesh Surapaneni, Xavier Brun, Brad Hamlin, “Methods of forming die structures with scalloped sidewalls and structures formed thereby,” Intel Corporation, US Patent Application US18/129,737, October 3, 2024.• Patent Application: Omkar G. Karhade, Harini Kilambi, Rajesh Surapaneni, et al, “Packaging Architecture For Wafer-scale Known-Good-Die Hybrid Bonding,” Intel Corporation, US Patent Application Jan 2, 2025.• Patent (Granted): Rajesh Surapaneni, Carlos Mastrangelo, “High-resolution flexible tactile imager system based on floating comb electrode,” University of Utah, U.S. Patent US95•••24, April 4, 2014.• Patent (Granted): Rajesh Surapaneni, Carlos Mastrangelo, “Microfabricated Flexible Ground Reaction Sensor Cluster for Navigation in GPS-Denied Environments”, University of Utah, U.S. Patent US86•••49 February 2, 2012.• Invited talk Sensors Conference 2013.• Process Engineering Skills: Process Development (Dry Etch; PECVD)| Process Integration | Program management | External customer engagement | Statistical Data Analysis | JMP Statistical Software | Design of Experiments (DOE)| Refined Problem Statements | Electrical Failure Analysis | X-SEM Analysis | Root Cause Analysis• Software Skills: SmartSheet | KLAYOUT | L-Edit | AutoCAD | Solidworks | COMSOL | Ansys | MS Office

Experience

1. Advanced Td Engineer

   Broadcom

   Jun 2025 — Present · Irvine, CA, US

Education

• University of Utah

  Doctor of Philosophy (PhD), MEMS, Sensors, Actuators

  2010 — 2013

• University of Utah

  Master of Science - MS, Mechanical Engineering

Skills

• Ansys
• Cvd
• Process Engineering
• Semiconductors
• Jmp
• Sensors
• Profilometer
• Solidworks
• Photolithography
• Design of Experiments
• Optical Microscopy
• Simulations
• Mems
• Etching
• Characterization
• Microfabrication
• Ellipsometry
• Matlab
• Comsol
• Scanning Electron Microscopy