Rajesh Suarada
Principal Engineer at Western Digital
- Role
- Principal Engineer at WD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Rajesh Suarada
Experience in Soc level verification using SV/UVM & Assembly Language-> Experience in Formal Verification using Jasper, IEV-> Complex Fabric Interconnect comprising of AXI,AHB & APB verified using IWB tool with Coverage-> Integrated/setup new VIPS with the existing Soc DV Env -> Experience in Gate Level Setup/Simulation/Debug-> Good experience on working with,PLL AMBA AHB, APB,AXI, I2C, UART,CAN, SPI,GPIO,SEC,PINT,PINMUX,SPU,SWU,CGU and others audio peripherals->Having Good experience in silicon validation and support for application team->Act as a DV Lead for 2 projects and completed the project on time and taped out successfully-> Involved in complete design cycle of a system which includes RTL Integration, Verification, Synthesis, STA and Board bring-up
Experience
Principal Engineer
Sep 2021 — Present · Bangalore Urban, IN
Education
Andhra University
Master of Science and Technology, VLSI Design
2008 — 2011
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