Rajesh Raj

About Rajesh Raj

In my current role, I am responsible for designing and implementing RTL (Register Transfer Level) code for high-speed SERDES (Serializer/Deserializer) PHY (Physical Layer) designs. My work involves developing and optimizing complex digital circuits to ensure robust performance and reliability in high-speed data transmission applicationsWorked as a Design Engineer 2 at Cadence Design Systems, specialized in high speed Serdes testing with controllers up to PCIe Gen5, FPGA based IP implementation and timing analysis, and testing with FPGA platforms. I have hands-on experience in the full life cycle of RTL/FPGA development, board design, system level testing, and debugging.I graduated with a Master of Technology degree in VLSI Design from National Institute of Technology Karnataka in 2019, where I worked on block level designs from concept design to implementation of blocks. I also have a Bachelor\'s degree in Electrical, Electronics and Communications Engineering from Punjab Technical University in 2015. I am proficient in Verilog/VHDL, TCL and batch file scripting, bare metal coding, and integration of IP in subsystems. I am passionate about designing and validating innovative and reliable digital circuits and systems.

Experience

1. Sr Silicon Design Engineer

   AMD

   Sep 2025 — Present · Hyderabad, IN

Education

• Punjab Technical University

  Bachelor's degree, Electrical, Electronics and Communications Engineering

  2011 — 2015

• National Institute of Technology Karnataka

  Master of Technology - MTech, VLSI Design

  2017 — 2019