Rajesh Kumar Tiwari

About Rajesh Kumar Tiwari

Overall, 20+ years of industry experience in chip design. Profound knowledge in the area of DFT architecture and implementation. Manage and lead team of 60+ engineers specialized in full chip DFT implementation and verification of different product line (Mobile, Modem, Compute, Automotive etc). Result-oriented professional with broad range of both technical and management skills. Manage SoC & Cores level DFT implementation, test mode timing constraint signoff and Insystem BIST methodology of Qualcomm Automotive designs.

Experience

1. Director of Engineering

   Qualcomm

   Apr 2024 — Present · Bengaluru, IN

   Key Responsibility:1. InSystem BIST Methodology for Automotive products - Boot KPI, HW/SW enabled BIST, Insystem Soft Repair, InSystem ATPG, On-Demand/Periodic BIST2. Engage with EDA R&D team to define and meet our requirement 3. DFT implementation - SoC and Core Level Scan implementation of all BDC designs4. TestMode constraint - Flat/hierarchical for test STA5. Cross team alignment/planning/mitigation to meet project schedule 6. Process Improvement, Enhancements, Left Shift initiatives7. Team/People management, project planning, execution

Education

• Malaviya National Institute of Technology Jaipur

  MTech, Electronics and Communication Engineering

  2002 — 2004

• Hindustan College of Science and Technology

  Bachelor of Engineering (B.E.), Electronics and Communication Engineering

Skills

• Bist
• Atpg, Memory Test, Low Power Dft, Bscan, Iddq, Analog Pmt, Burnin
• Arm Architecture
• Memory Test
• Cadence
• Ic
• Spyglass
• Rtl Design
• Scan Architecture
• Verilog
• Low Power
• Tetramax
• System on a Chip (Soc)
• Low-Power Design
• Application-Specific Integrated Circuits (Asic)
• Soc
• Static Timing Analysis
• Very-Large-Scale Integration (Vlsi)
• Dft
• Test Mode Security
• Vlsi
• Rtl
• Debugging