Rajesh Kumar
Physical Design Lead
- Role
- Senior Principal Engineer at Arm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Rajesh Kumar
RTL to GDSIISpecialties:* Full chip/Block level PNR - Hierearchical design partition, IO ring planing, Timing budgeting,floorplaning,powerplaning,placement,CTS & routing,STA + SI signoff.[Magma/Astro/PTSI/Celtic]*DFM & EM * Full Chip physical verification - Calibre/Hercules* Technology - 12nm,16nm,28nm,40nm,65nm & 130nm*Verilog RTL coding, simulation, synthesis & FPGA/Post silicon validation.
Experience
Senior Principal Engineer
Jul 2024 — Present
Education
Madurai Kamaraj University
B.E, Engineering
1998 — 2002
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