Rajesh Gottumukkala

About Rajesh Gottumukkala

Profound Knowledge in DFT and STA domains. Proven track record of execution on-time and first pass silicon. Excellent knowledge and hands-on experience in adjoining domains of RTL & Aware DFTTest Power/Test Time Reduction and Test Quality ImprovementStatic Timing Analysis and Timing ClosureRTL Integration and Power ManagementSTA Constraints SignoffAutomation and Execution EfficiencyTeam Building

Experience

1. Senior Engineering Manager

   Google

   Oct 2020 — Present · Bengaluru, IN

   Leading DFT Methodology & DFT CAD in Silicon team- Led SoC DFT in Next Generation Mobile SoC

Education

• International Institute of Information Technology Hyderabad (IIITH)

  M.Tech, VLSI and Embedded Systems

  2004 — 2006

• Gowtham Junior College

  Intermediate, MPC

  1998 — 2000

• B.R.M.V.M.High School

  Secondary Education

  1993 — 1998

• Jawaharlal Nehru Technological University

  B.Tech, Electronics and Communication Engg

  2000 — 2004

Skills

• Physical Design
• Soc
• Debugging
• Low-Power Design
• Arm
• Functional Verification
• Asic
• Bist
• Silicon Debug
• Verilog
• Vlsi
• Dft
• Atpg
• Fishtail
• Rtl Design
• Spyglass
• Static Timing Analysis