Rajen Paudel
Design Verification Engineer @Apple
Munich, DE
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Jun 2017 — Present
Design Verification Engineer @Apple
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Munich, DE
EDUCATION
2007 — 2011
Maulana Azad National Institute of Technology
Bachelor's Degree, Electronics and Communication
2004 — 2006
St. Xavier's College
High School, Science
2013 — 2015
Technical University of Munich
Master's Degree, Electrical, Electronics and Communications Engineering
SKILLS
Physical DesignStatic Timing AnalysisLogic SynthesisClock Tree SynthesisTclVerilogVlsiSocRtl DesignFunctional VerificationModelsimAnalogMatlabPcb DesignVhdlUniversal Verification Methodology (Uvm)Open Verification MethodologyPerlXilinxCadenceIntegrated Circuit DesignAnalog Circuit DesignMixed-Signal Ic DesignLow-Power DesignCmosSignal IntegrityCC++Rtl CodingMixed SignalMicroprocessorsDigital ElectronicsTiming ClosureComputer Architecture
ABOUT RAJEN PAUDEL
Interested in Low Power System on Chip Technologies and Mixed Signal Design.Specialties: • 2 Years of experience in Synthesis & STA and Physical Design (RTL to GDSII) • 2 Years of experience in Functional Verification(OVM/UVM Methodology, Constrained Random Verification and SVA)• Good understanding and experience on ASIC design and Low Power Implementation
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