Rajendra Shekhawat

About Rajendra Shekhawat

Seasoned verification engineer with expertise in IP subsystem and SOC design verification 14+ years of experience in IP, subsystem and SOC design verification. Experience in VMSA architectural verification of ARMV8 A-profile CPU, CPU subsystem verification using perspec, Coherency verification, UPF based low power verification of ARM A-profile CPU cluster at soc level, AXI interconnect design verification. Good understanding of processor microarchitecture, coherency concepts. Experience in developing verification strategies, comprehensive test plans and test benches to verify the designs. Experience in developing VIPs as well as Integrating VIPs into test benches. Experience in developing constrained random test cases, directed test cases and co-sim test cases Proficiency in debugging co-sim and hardware design issues as well as test bench issues. Experience in developing functional coverage. Utilising functional and code coverage analysis to identify and address test plan or test case gaps. Elementary exposure to formal verification using Jasper Gold. Experience in power aware verification with UPF. Demonstrated leadership skills by effectively delegating tasks and scheduling work, as well as providing training to new employees. Experience of working in geographically dispersed teams. Skills Set | AMBA bus protocols (i.e. Axi, Apb)| Low power verification using UPF | IOSF (Intel on chip fabric)| Processor architecture | Armv8 (i.e. VMSA)| Universal Verification Methodology (UVM)| Constrained Random Verification | Register Abstraction Level | Unified Power Format (UPF)| Formal Property Verification (FPV)| System Verilog | Verilog | VHDL | C | Python scripting | Shell scripting | ArmV8 ISA | VCS | Verdi | DVE | Git | Netbatch | LSF | Gerrit | Hudson (Intel)| Gatekeeper (Intel)| Jira l Perspec Always interested in exciting and challenging opportunities.

Experience

1. Design Verification Engineer

   Google

   Jun 2023 — Present · Bengaluru, IN

   CPU subsystem,SoC Verification

Education

• Ymca University of Science and Technology

  Bachelor of Technology (B.Tech.), Electronics instrumentation and control

  2007 — 2011

Skills

• Functional Verification
• Microcontrollers
• Ethernet
• Various Peripheral Protocols (I.e. Nand Flash, I2c, Uart, Ssp)
• Lsf
• C
• Hdls (I.e. System Verilog, Verilog, Vhdl)
• Operating Systems (I.e. Linux, Windows)
• Verilog
• Vmm
• Soc
• Vhdl
• Hudson
• Assembly Languages (I.e. Arm Core, 8086, 8085, 8051)
• Network Interconnect Verification
• Low Power Verification of Arm Cluster
• Asic
• C++
• Tools (I.e. Vcs, Ncsim, Dve, Simvision, Modelsim, Quartus, Cvs, Svn, Dssc and Gi
• Verification Methodologies (I.e. Crv, Vmm, Ral, Upf)
• Digital Design (Basic Concepts and Design)
• System on a Chip (Soc)
• Pcie
• Systemverilog
• Scripting Languages (I.e. Perl, Shell)
• Debugging
• Verification Languages (I.e. C++, C)
• Amba Bus Protocols (I.e. Axi, Ahb, Apb, Ace)
• Linux
• Soc Verification
• Axi