Rajeev Ranjan

About Rajeev Ranjan

Area of Interest: Physical design, STA, ASIC Design, Semiconductors. Worked on accomplishing Placement & Routing of block in 2nm 3nm 5nm 7nm 12nm 28nm Comprehensive understanding of backend flow such as Floor-Planning, PNR, CTS. Good understanding of Static Timing Analysis. Familiar with Different Sign off checks. Ability of Debugging Bugs. Ability to solve problems & collaborate effectively. Strong fundamental knowledge of semiconductor concepts.I have good understanding of Physical Design,STA, VLSI Design Concepts. I have excellent interpersonal and communication skills.I would describe myself as a motivated, hard working and ambitious individual with an aptitude of always looking to learn new things

Experience

1. Staff Engineer

   Arm

   Apr 2025 — Present · Bangalore Urban, IN

Education

• Visvesvaraya National Institute of Technology

  Master’s Degree, VLSI DESIGN

  2014 — 2016

• Saint Soldier International School, Chandigarh

  High School

Skills

• Xilinx Ise
• Analog Circuit Design
• Cmos
• Linux
• Modelsim
• Cadence Virtuoso
• Cadence Rtl Compiler
• Cadence
• Very-Large-Scale Integration (Vlsi)
• Verilog
• C
• Vlsi
• Physical Design
• Cadence Encounter
• Vhdl
• Mixed Signal
• Rtl Design
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Spice
• Innovus
• Asic
• Design Rule Checking (Drc)
• Eldo
• Mixed-Signal Ic Design
• Genus
• Layout Versus Schematic (Lvs)
• Matlab