Rajeev Varshney

About Rajeev Varshney

Senior ASIC/RTL Design Engineer with 12 years of experience and 8+ years executing full RTL-to-GDSII flows for 10+ Data-center, Mobile, and Broadcast SoCs—achieving aggressive PPA goals through low-power microarchitecture and IP-level optimizations. Designed a datapath backup solution for shutdown mode, achieved 2% power saving by developing SRAM power-down mechanism. Delivered PPA-optimized NoC interconnects across multiple SoCs, and improved device/peripheral access latency by re-architecting key NoC paths and optimizing interconnect pipelines. Reduced mismatch-driven incremental releases by 30% by implementing automated RTL–spec alignment flow, interface consistency checks, and early quality gates. Created XLS-based DV configuration flows for NAND Flash devices, partnering with CAD, reducing DV dependency for silicon-dump recreation, and accelerating verification cycles substantially. Led constraint development, STA, and low-power analysis for 5+ SoCs with distinct timing, frequency, and integration requirements—consistently achieving first-pass timing closure at both IP and chip level. Skilled in verification/debug, including silicon debug analysis, testbench development, and design validation. Automated CDC flows for 50+ NoC IPs and developed Perl-based SoC MUX connectivity validation tools to prevent integration issues. Proven team leader and mentor, supporting onboarding, guiding contractors, and improving design execution efficiency.

Experience

1. Silicon Design Engineer

   Google

   Jun 2022 — Present · Bengaluru, IN

Education

• DRONACHARYA COLLEGE OF ENGINEERING , GREATER NOIDA, G.B.NAGAR

  Engineer’s Degree, Electrical, Electronics and Communications Engineering

  2007 — 2011

• Centre for Development of Advanced Computing (C-DAC)

  PG DIPLOMA- CDAC, VLSI

Skills

• Rtl Design
• Tcl
• System Verilog
• Digital Circuit Design
• Digital Ic Design
• Amba Ahb
• C
• Cdc
• Application-Specific Integrated Circuits (Asic)
• Axi
• Dft
• Very-Large-Scale Integration (Vlsi)
• Verilog
• Logic Synthesis
• Static Timing Analysis
• Linux
• Shell Scripting