Rajeev Ranjan
Packaging R&D Engineer at Intel Corporation
- Role
- Packaging R & d Engineer, Substrate Pathfinding Integrator at Intel
- Location
- Phoenix, AZ, US
- LinkedIn followers
- 500 followers
About Rajeev Ranjan
Experienced Research and Development Engineer in semiconductor substrate packaging industry with strong technical and communication skills.Ph.D. in Chemistry from Arizona State University.
Experience
Packaging R & d Engineer, Substrate Pathfinding Integrator
May 2017 — Present
Education
Arizona State University
Doctor of Philosophy (Ph.D.), Chemistry
2008 — 2014
Delhi University
Bachelor of Science (BSc), Chemistry
2003 — 2006
Indian Institute of Technology, Delhi
Master of Science (MS), Chemistry
2006 — 2008
Skills
- Nanomaterials
- Ir
- Reverse Micelle
- Dls
- Inorganic Synthesis
- Materials Science
- Organic Chemistry
- Electrochemical Characterization
- R&D
- Tem
- Hplc
- Pxrd
- Karl Fisher
- Cyclic Voltammetry
- Nanotechnology
- Experimentation
- Microsoft Office
- Tga
- Nanoparticles
- Gas Chromatography
- Fluorescence Spectroscopy
- Ionic Liquids
- Nmr
- Organic Synthesis
- Mass Spectrometry
- Science
- Spartan
- Schlenk Line
- Chemistry
- Ftir
- Sem
- Powder X-Ray Diffraction
- Inorganic Chemistry
- Uv/Vis
- Gc-Ms
- Fluorescence
- Eds
- Characterization
- Spectroscopy
- Electrochemistry
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.