Rajeev Puppala
Principal Engineer @ Cadence Design System
- Role
- Principal Application Engineer at Cadence
- Location
- Nizamabad, TG, IN
- LinkedIn followers
- 500 followers
About Rajeev Puppala
PPA benchmarking for high performance CPU/GPUs Experience in backend Physical Design planning, Placement, CTS, Routing, Timing closure, Sign-off fixes & IR/EM Fixes. Worked on Multi-voltage based designs, Low power checks for CPU/GPU (PCIESS) based designs. Hands on experience with Synopsys & Cadence EDA tool set. Worked with various technology nodes like 3n, 5nm, 6nm,10nm,16nm,28nm,40nm & 90nm technology nodes with TSMC & Intel foundry.
Experience
Principal Application Engineer
Sep 2022 — Present · Hyderabad, IN
PPA push for complex processors
Education
Shanthinikethan High School
High School, Maths & Physics
2001 — 2003
Vijay Rural Engineering College - Nizamabad
Bachelor’s Degree, Electronics and Communications Engineering
2005 — 2009
SNIST/JNTU Hyderabad
Master of Technology (M.Tech.), VLSI & ESD
2010 — 2012
Shanthi Jr. College, Armoor
Intermediate, MPC
2003 — 2005
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