Rajdeep Mazumder

About Rajdeep Mazumder

As a Physical Design Engineer at Intel, I am part of a team working tirelessly to enable the Silicon Armstrong era for the world. I work with complex designs, tools, and methodologies to deliver full-chip with zero-silicon issues for Tape outs. I have in-depth experience in sub10nm design with solid debugging skills for layout verification, ECOs and Layout design automation to reduce turnaround time.I hold a Master of Technology in RF Design and Technology from IIT Delhi.I am passionate about sharing my knowledge and guidance with students who aspire to join the VLSI industry through my YouTube channel, whyRD. I am also a daily meditator and a lover of India\'s spirituality.

Experience

1. Physical Design Engineer

   Intel

   Jul 2021 — Present · Bengaluru, IN

   We drive new process nodes to maturity via multiple iterations of test chip development for external and internal Intel Foundry customers. I have Owned multiple high-performance test chip Full Chip Integration, layout modification and Signoffs for Tape-outs ranging from intel16 to intel18A nodes, with powerVia to support back metal power delivery Additional responsibilities include physical verification(DRC.LVS, ANT, ERC and all other checks for zero silicon issues), Floor planning, closing blocks till the cell-all clean, guiding the MDs to get rid of error seen from Full chip with minimal manual iteration. Also helped drastically reduce custom layout Design time with Layout automation using SKILL(Cadence proprietary scripting language) and TCL

Education

• National Institute of Technology Silchar

  Bachelor of Technology - BTech, Electronics and Communications Engineering

  2013 — 2017

• Indian Institute of Technology, Delhi

  Master of Technology - MTech, RF Design and Technology

  2019 — 2021