Rajbul Biswas

About Rajbul Biswas

A committed and competent Electronics and Communication Engineer in the VLSI Field with 7 years 8months rich experience.Hands on experience in ASIC RTL Design in Verilog. Hands on experience to build architecture to keep in mind area, power and timing budget. Hands on expreciene in Lint and Front End synthesis. Have a good knowledge in CADENCE HAL tool for lint. Have a good knowledge on CADENCE GENUS and SYNOPSIS FC tool for Front End Synthesis. Hands on experience in scripting language like Perl and TCL. Have a knowledge in C, C++ and system verilog. Hands on experience on UPF and VCLP.Hands on experience on Power Management Design implementation. PKGC6 active power management and idle power management.Hands on experience on Fishtail tool for sdc constraints promotion.Hands on experience on intel caliber toolHands on experience on Spyglass CDC/RDC

Experience

1. Soc Design Engineer

   Intel

   Jan 2024 — Present · Bengaluru, IN

Education

• Jalpaiguri Government Engineering College

  B.Tech

  2013 — 2017