Rajasekhar Vazrala
CPU Cache Design Verification Engineer
- Role
- Senior Design Engineer at AMD
- Location
- Fort Collins, CO, US
- LinkedIn followers
- 500 followers
About Rajasekhar Vazrala
ASIC/SOC Design and Verification Engineer with experience in micro-architecture development, RTL design, and functional verification of complex designs. Currently working on performance verification of L2/L3 caches of next gen AMD server class processors.
Experience
Senior Design Engineer
May 2021 — Present · Fort Collins, CO, US
Education
Jawaharlal Nehru Technological University
Bachelor of Technology (B.Tech.), Electrical and Electronics Engineering
2009 — 2013
University of Utah
Master's degree, Electrical and Computer Engineering
2015 — 2017
Skills
- Cadence Schematic Capture
- C++
- Python
- Sql
- Linux Kernel
- Linux
- Modelsim
- Xilinx Ise
- Electrical Design
- Embedded C
- Rtl Design
- Rtl Verification
- Device Drivers
- Xilinx Zynq Fpga
- System on a Chip (Soc)
- Field-Programmable Gate Arrays (Fpga)
- C
- Programming
- Core Java
- Debugging
- Program Management
- Computer Architecture
- Power Systems
- Electrical Machines
- Power System Operations
- Very-Large-Scale Integration (Vlsi)
- Management Consulting
- Embedded Linux
- Logic Synthesis
- Fpga Prototyping
- Application-Specific Integrated Circuits (Asic)
- Vlsi Cad
- Strategic Planning
- Microsoft Office
- Firmware
- Java
- Xilinx Vivado
- Verilog
- Power Electronics
- Synopsys Primetime
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