Rajat S.
Lawrence Livermore National Laboratory
Livermore, CA, US
EMAILS
MOBILE NUMBERS
+19•••••••47
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WORK HISTORY
Present
@Lawrence Livermore National Laboratory
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SKILLS
PrimetimeLogic SynthesisRtl DesignFormal VerificationAnalog Circuit DesignDigital Signal ProcessingFunctional VerificationSystemcMatlabLow-Power DesignI2cSimulationsPythonPerlUvmPower AnalysisStatic Timing AnalysisSynopsys ToolsC++SystemverilogCmosDesign VerificationFpgaPllTclField-Programmable Gate Arrays (Fpga)Circuit Design
ABOUT RAJAT S.
I do embedded designs in FPGA and Microcontrollers, and have both ASIC and FPGA…
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