Rajat Garg
SRAM Memory Layout Engineer | Advanced Node Expertise (2nm, 3nm and 22nm) | GAAFET, FinFET, and planar CMOS | Custom Design and Automation
- Role
- Memory Layout Engineer at Broadcom
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Rajat Garg
Memory Layout Engineer with 4 years of experience in full-custom/compiler SRAM/RF layout at advanced nodes (2nm, 3nm, and 22nm). Skilled in Periphery logic design (Centres, IOs etc.), DRC/LVS closure, ERC/DFM compliance, Rescheck, PPA optimisation, Matching and Shielding. Experienced in Synopsys Custom Compiler, ICV verification, and cross-domain collaboration with circuit design teams. Keen to expand into Memory Layout/ Analog Layout/ Compiler development and flow automation roles. Open to look for roles that give exposure to strengthening scripting fundamentals (SKILL/Tcl/Python) to bridge layout and CAD.
Experience
Memory Layout Engineer
Feb 2026 — Present · Bengaluru, IN
Education
Aligarh Muslim University
Bachelor of Technology, Electronics Engineering
2018 — 2022
Our Lady of Fatima High School
High School
2003 — 2015
Saiyyid Hamid Senior Secondary School
Higher Secondary, Mathematics and Science
2015 — 2017
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