Rajat J.

About Rajat J.

I am a graduate from Thapar university Patiala, batch of 2015 and currently working in AMS -DAC group at ST Microelectronics.My skill-set include:Understanding of SoC architecture and Verification Methodology and associated flow.Understanding of SoC integration and UVM testbench.Experience with Verification of ARM v8 based Debug Architecture.Knowledge of AMBA bus protocol (APB, AHB, AXI) and Freescale internal protocol for on-chip communication and SoC control.Experience with UVM, ability to code independently using SV-UVM methodology as a part of test sequences and testbench development.Experience with writing System Verilog Assertions.Experience with writing and maintaining Perl and Shell scripts for flow automation andExperience at working in Unix/Linux environment.Strong hold on Verilog and RTL debugging.Experience with RTL simulation using VCS and waveform Debugger DVE(Synopsys).Understanding of DPI for interfacing SystemVerilog and C.I have strong interpersonal skill, enabling me to work effectively within a team and a zeal to learn and unlearn new things everyday.

Experience

1. Senior Staff Engineer

   意法半導體

   Feb 2026 — Present

Education

• Thapar Institute of Engineering and Technology

  Bachelor's degree, Electrical, Electronics and Communications Engineering

  2011 — 2015