Rajapavan Venishetti

About Rajapavan Venishetti

As a System Validation Engineer at Intel, my focus is on ensuring our technology\'s utmost…

Experience

1. System Integration and Validation Engineer

   Intel

   Dec 2021 — Present · Hillsboro, OR, US

   Supported the first silicon Bring-Up boot initiatives, overseeing the Security and ManageabilityFeature enablement on Intel client and Workstations devices with Microsoft Windows OS. Collaborated closely with SOC design teams to ensure validation and readiness for Security & Manageability Functional testing and debug post silicon issues. Crafted and implemented detailed verification testing frameworks, meeting all key Qualityrelease milestones criteria. Executed rigorous verification tests utilizing automation tools alongside hands-on assessmentswhich enhanced overall efficiency for each BKC run by reducing test cycle time. Automated validation processes and scripted small tools to reduce manual overhead andaccelerate test cycles. Optimized BKC Test Content and Improved Test latency. Led a team of 6 members during SOC FW/post-si validation efforts of Granite RapidsPlatform(GNR), ensuring all Quality release milestones criteria are met. Led hardware debug efforts on GNR Silicon validation for Security IPs including Intel Boot Guard,Intel TXT, and TPM integration; identified root causes of post-silicon failures and worked withBIOS and design teams to drive resolution. Triaged hardware anomalies impacting Manageability features such as Intel AMT and RemotePlatform Erase; resolved bugs related to ME firmware interaction and ensured feature stabilityunder stress and power cycles. Primary point of contact for BIOS to implement security and manageability features and debugissues, collaborating with 3 cross-functional teams to address defects and improve systemintegrity.