Rajanikanth D

About Rajanikanth D

14+ years of experience in semiconductor industry which includes 8 years of experience in VLSI CAD tool and flow development aimed at simplifying Test, Verification, and DFT activities of an SoC, and 6+ years of experience in RTL development, Test, Verification, DFT activities of Complex IP\'s and SoC along with silicon debug. In depth, and detailed understanding of DFT and Functional testing techniques involving Scan, Loopback tests, BIST, 1500, 1149.1 Boundary Scan & JTAG, and Clock/Reset management.Career Goal : Technical leader in the area of SoC / IP Design, and its Test, Verification, DFT methodology. I would like to part of an organization which would challenge my: Hardware and Software Design Skills, Test Expertise, Experience, Execution, and Methodology Development in terms of Tool and Flow design.Specialties: RTL development, Test, Verification, DFT specification, planning, and execution on complex IP\'s and SoC’s. Scan Insertion, ATPG stuck-at, and transition fault testing. 1500 RTL development, Loopback BIST, Memory BIST and Boundary Scan. Quick and smart scripts / tools to aid in Test, Verification, DFT execution.

Experience

1. Senior Dft Engineer

   Intel

   Apr 2018 — Present · IN

Education

• Acharya Nagarjuna University

  B. Tech., Computer Science

  1994 — 1998

• Nirmala High School, Machilipatnam

  Secondary School, Schooling

  1981 — 1991

• Indian Institute of Technology, Madras

  M.Tech, Computer Science

  1998 — 2000

Skills

• Purify
• Testing
• Lsf
• Less
• Simulations
• Jtag
• Debugging
• C++
• Lec Equivalence
• C
• Vlsi
• Verilog
• Application-Specific Integrated Circuits (Asic)
• Purecov
• Atpg
• Perl
• Product Engineering
• Tetramax
• System on a Chip (Soc)
• Post Silicon Debug
• Boundary Scan
• Asic
• Rtl Design
• Static Timing Analysis
• Synopsys Tools
• Ieee 1500
• Compilers
• Design for Manufacturing
• Very-Large-Scale Integration (Vlsi)
• Dft
• Spyglass
• Loop Back Tests
• Swig
• Perl Code Coverage
• Clearcase
• Soc
• Emacs