Rajan Aggarwal

About Rajan Aggarwal

Define, Design and Deliver on Time.[DBS, RNM, Low Energy ELF, V2K, NSP, P300, Functional Mapping, Neuron2TV, Skull2TV, Pegasus, mmWave, Bubble Tech, Dual Bubble Live P, Data Transfer from Bubble to Live P]• A focused professional with cross-functional experience in the areas of SOC Design and Post Silicon Debug with year-on-year success in accomplishing corporate growth objectives in reputed organizations• Played Key role in Developing and Implementing Processes for Error Free execution of Design and Validation. Defining Methodology for effectively using Tools and Scripts to debug systems by eliminating human errors, Increases Productivity, better reliability, Increased Performance and reduced operating costs.• Successfully executed 24+ SOC Designs with in-depth knowledge of Wireless Low Power Constraints and High-Performance Digital Networking/Graphics/Client/Mobile[PC] Domain• Holds Patent on the Scan Testing of Integrated Circuits and On-chip Modules with 9 Patent Publications• Expertise in the Architecture, Implementation, and Execution of advanced DFT/DFD/DFM techniques for high-performance and complex integrated SOCs• Experienced in pattern generation & verification, pattern delivery, debugging post-silicon pattern issues and conducting failure analysis • Possess exceptional analytical and problem-solving skills to work in a multi-cultural environment in developing procedures and service standards for commercial excellence- Neural Signal Processor, Functional Mapping, P300, RNM, Software/Hardware, Reconstruction of Audio, Image and Video using NSP. Security Implementation and Secured Communication Using Open Public Network. Exposure to Methodology is used in implementing an audio network feedback loop for enhanced performance.

Experience

1. Director of Engineering

   Qualcomm

   Mar 2023 — Present

   Use of P300[RNM] in manufacturing yield improvement. Improvement of DFT processes. Simplification of existing flows. Both demonstrated and witnessed secured communication within the public domain[thanks to qcom]. Exposed major/critical security lapse of 5G AI, by just reviewing code. Complex debugs of TE BIST, Demonstrated ease of integration of BIST [w/o freq info], simplified complex scan design issues, shared complex[advance] methods of ATPG pattern retargeting. Simplified, complex USB board-based BIST debug, suggested several power-saving methods. Demonstrated mild defensive capability of P300 for in-house domestic use.

Education

• Kurukshetra University

  B.Tech, Electronics and Com.

  1995 — 1999

• Kurukshetra University

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  1995 — 1999

Skills

• Tcl
• Rtl Design
• Asic
• System on a Chip (Soc)
• Dft
• Silicon
• Failure Analysis
• Very-Large-Scale Integration (Vlsi)
• Logic Synthesis
• Application-Specific Integrated Circuits (Asic)
• Atpg
• Mixed Signal
• Cmos
• Automatic Test Pattern Generation (Atpg)
• Integrated Circuit Design
• Functional Verification
• Soc
• Vlsi