Rajan Pethukkani
Dft Engineer for Google @HCLTech
Cambridge, GB
EMAILS
MOBILE NUMBERS
+91 *********19
Signup · Get unlimited contacts
WORK HISTORY
Jan 2024 — Present
Dft Engineer for Google @HCLTech
View department →
Chennai, IN
Scan Insertion using FC and genus.Scan insertion for blocks with DDR IP.IJTAG verification.Test constraints check for STA using PrimetimeATPG for stuckat and Transistion delay fault models using tessentGatelevel simulations for unit delay and SDFMBIST gate level simulations
EDUCATION
N/A
Kamaraj College of Engineering and Technology
Bachelor of Engineering - BE
ABOUT RAJAN PETHUKKANI
Backend experience: MBIST insertion Scan insertion using Synopsys DC/FC compilier…
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.