Raja Kanagala

Experience

1. Senior Product Engineering Group Director

   Cadence

   Oct 2020 — Present

   Managed technical Innovations in digital space for the last 10 years, including synthesis in the last 2 years.• Responsible for development and architecture of timing closure environment in Innovus• Recruited and managed a world class engineering team that spans across the globe• Owner of key parts of Innovus from hierarchical database, partitioning, pin assignment, time budgeting, low power, ILM infrastructure and design abstraction using reduced data set.• Implemented and managed physical design for high speed, low power SoC, GPU and CPU’s

Education

• Louisiana Tech University

  M.S, EE

  1995 — 1996

• Osmania University

  Engineering, Electronics & Communications

  1991 — 1995

• San José State University

  M.S, EE

  1996 — 1997

Skills

• Signal Integrity
• Cadence Virtuoso
• Eda
• Tcl
• Application-Specific Integrated Circuits (Asic)
• Static Timing Analysis
• Timing
• Asic
• Vlsi
• Timing Closure
• Cmos
• Perl
• Physical Design
• Physical Verification
• System on a Chip (Soc)
• Soc
• Clock Tree Synthesis
• Parasitic Extraction
• Logic Synthesis
• Floorplanning
• Low Power Design
• Routing
• Low-Power Design
• Lvs
• Drc
• Microprocessors
• Ic