Raj Bharadwaj

About Raj Bharadwaj

Expert in Low power technologies, viz: Adaptive Voltage Scaling, Adaptive/Dynamic Voltage and Frequency Scaling, Hardware Autonomous Power Gating etc. Physical Design/Timing closure expertise for low power and/or high performance processor design. Physical Design Enabler for 28nm Leakage Management Techniques Skilled in Advanced Technology Development/Interconnect Scaling FPGA-ASIC based system design. Communication ASIC/System design (e.g SDH/SONET). Past experience in Xilinx, CDOT-NewDelhi, Vitesee, NJ etc

Experience

1. Master Engineer (Low Power, Design Technology)

   Broadcom

   Mar 2016 — Present · Irvine, CA, US

   Drive technology/tools for System Power Modeling, Power Analysis & CMOS power scaling- System Margin optimization for power/performance trade-offs- AVS - characterization, hardware implementation and system architecture- Process technology readiness, Yield enhancement

Education

• The University of Texas at Dallas

  Ph.D, Electrical and Electronics Engineering

  2001 — 2006

• Motilal Nehru National Institute Of Technology

  B.S, Electrical Engineering

  1995 — 1999

• The University of Texas at Dallas

  M.S, Electrical Engineering

  2001 — 2003

Skills

• Embedded Systems
• Eda
• Semiconductors
• Hardware Architecture
• Rtl Design
• Physical Design
• Physical Verification
• Soc
• Technology Scaling Entitlement
• Debugging
• Power Management
• Timing Closure
• Formal Verification
• Vlsi
• Adaptive Voltage Scaling
• Static Timing Analysis
• Verilog
• Ic
• Asic
• Xilinx
• Scalability