Raj K.

Design Verification Engineer || Worked with leading companies like NVIDIA, Texas Instruments

Role
Design Verification Engineer at Texas Instruments
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers

About Raj K.

ASIC Verification Engineer with 4+ years of experience, specializing in SystemVerilog (UVM) based testbench development and debugging. • have contributed to successful project deliveries for leading semiconductor companies like NVIDIA and Texas Instruments. • Technical Skills: Proficient in Verilog, SystemVerilog, Perl, Shell, with expertise in Questasim, VCS, Simvision, and Perforce, Jenkins, DSSC. • Protocol Expertise: Hands-on experience with PCIe (Gen6 & Gen5), AXI, SPI, I2C. • Experience with Test Automation: Expertise in developing constrained random test cases and directed tests for coverage closure. • Collaboration and Mentoring: Worked closely with design and architecture teams, mentored interns, and contributed to test plan strategies. • Educational Background: Postgraduate Diploma in VLSI from CDAC (2020) and B.Tech in Electronics and Communication from St. Francis Institute of Technology (2019). • Problem-Solving: Strong debugging skills, test development, and coverage analysis for functional and code coverage closure. • Hands-on with Verification Methodologies: Extensive experience in UVM-based testbench architecture and protocol-specific testing.

Experience

  1. Design Verification Engineer

    Texas Instruments

    Aug 2024 — Present · Bengaluru, IN

    Verified straps configurations, ensuring proper initialization of registers and deserializer functionalityunder default settings. Developed and executed tests for ROM memory verification to ensure integrity and proper firmwareloading/execution. Implemented and validated MBIST test (Memory Built-In Self-Test) to ensure robustness and reliability ofinternal memories. Wrote System Verilog assertions to validate reset behavior, state machine transitions, and error flaggeneration for design compliance. Achieved comprehensive coverage through directed and constrained random test cases.

Education

  • Centre for Development of Advanced Computing (C-DAC)

    PG-VLSI, VLSI

    2019 — 2020

  • Shri Bhagubhai Mafatlal Polytechnic

    Diploma in Industrial Electronics, Industrial Electronics

    2012 — 2016

  • St. Francis Institute Of Technology

    Bachelor's degree, electronics and telecommunication engineering

    2016 — 2019

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Raj K. — Design Verification Engineer at Texas Instruments in Bengaluru, KA, IN | Unifers