Rahul Teradal
DV Engineer| Verilog | SystemVerilog | UVM | Digital Electronics | GATE 2024 Qualified | IIT-Certified | Open for Full-Time Roles | Immediate Joiner
- Role
- Manuscript Reviewer at Elsevier
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
Writing/EditingView LinkedIn profile
About Rahul Teradal
GATE-Qualified Design Verification Engineer (ECE)| UVM • SystemVerilog • RTL • SoC…
Experience
Manuscript Reviewer
Sep 2024 — Present
Education
MORARJI DESAI RESIDENTIAL PRE UNIVERSITY SCIENCE COLLEGE NIDASOSI
Intermediate level education
2020 — 2021
JAIN COLLEGE OF ENGINEERING AND RESEARCH UDYAMBAG (BELAGAVI )
Bachelor of Engineering - BE
2021 — 2025
MORARJI DESAI RESIDENTIAL SCHOOL SADALAGA
SSLC
2018 — 2019
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