Rahul Kalambe

About Rahul Kalambe

Working as SoC Design Engineer in Full Chip Timing (STA). Responsibilities- Full-Chip Timing closure and Signoff- DFX Timing- SoC BE Clocking- Signal Integrity and Noise- Block-level implementation- PCie Gen4/Gen5 Subsystem and SoC level Timing Signoff.Worked as Design Automation Engineer in Intel for 3 years. Was responsible for automation of tools used for Analog Circuit Simulations, Parasitic Extraction using STAR-RC, Std-cell characterization and Signal Integrity/Noise analysis.Worked as Analog Mixed Signal Design Engineer in Semtronics MicroSystems Pvt. Ltd. Bangalore from Jan 2011-July 2011.Skills: Design Automation. Implementation, Timing signoff (STA), Signal Integrity & Noise.

Experience

1. Sta Lead & Engineering Manager

   Intel

   May 2021 — Present · Hillsboro, OR, US

   Full-Chip Timing Convergence & signoff for Intel\'s Client SoC- SoC Clocking from BE perspective- PV Methodology- Constraint development for robustness, quality and runtime improvements- Constraints Promotion, Demotion, Verification using TCM (Fishtail)- DFX and functional topologies planning for SoC- Full-Chip Timing closure and Signoff; Hierarchical Timing Analysis- Signal Integrity and Noise.

Education

• National Institute of Technology Warangal

  Master of Technology, VLSI System Design

• Nagpur University

  Bachelor of Engineering, Electrical, Electronics and Communications Engineering

Skills

• Pv
• Noise
• Tcl
• Perl Script
• Perl Automation
• Perl
• Eda
• Rv
• Simulations
• Vlsi