Rahul Agarwal
Staff Engineer at Samsung Semiconductor India R&D (SSIR)
- Role
- Staff Engineer at Samsung Semiconductor
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Rahul Agarwal
Specialize in physical design and signoff closure at the SoC level, managing multi-hierarchical partitions across 3nm, 4nm, 5nm, and 7nm technologies.My expertise includes floorplan and partitioning, IP/GPIO/BUMP planning and RDL routing for big die SoC designs. Handling DRC, LVS, PERC, and DFM closure at SoC level.I did MTech in Microelectronics from BITS Pilani and BTech in ECE from Indian Institute of Information Technology, Allahabad, and working as Staff Engineer at Samsung Semiconductor India R&D (SSIR).I am a dedicated engineering professional with a deep passion for technology.
Experience
Staff Engineer
Mar 2025 — Present · Bengaluru, IN
Education
Delhi Public School, Yamunapuram
Intermediate, PCM + CS
2010 — 2014
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Microelectronics
Indian Institute Of Information Technology Allahabad
Bachelor of Technology (B.Tech Honors) , Electronics and Communication Engineering
2015 — 2019
Skills
- Management
- C++
- Cadence Schematic Capture
- Operating Systems
- Java
- Antennas
- Xilinx Ise
- Matlab
- Vlsi Cad
- Analog Circuit Design
- Leadership
- Team Management
- Html
- C
- Programming
- Microsoft Office
- Computer Networks
- Very-Large-Scale Integration (Vlsi)
- Digital Electronics
- Cadence Virtuoso Layout Editor
- Sql
- Modelsim
- Cadence Virtuoso
- System Verilog
- Xilinx Vivado
- Asic Verification
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