Rahul Varma K
SoC Design Engineer
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Rahul Varma K
ß 4+ years of experience as Product and Test Development Engineer and knowledge in all aspects of semiconductor test including silicon bring-up, highvolume ATE production and system testß Experience in Advantest V93K, Teradyne I-Flex and LTX Fusion tester platformsß Expertise in all hardware and software aspects of test engineering,C++ and Pythonß MBIST/ATPG/SCAN pattern debug and DFT basic architecture knowledgeß Good experience in Analog/Mixed Signal Design and Layoutß Experience in layout and Verification of Analog Blocks, having worked in both Cadence CDB andOA Layout Databasesß Masters in Microelectronics from MIT,Manipal(2009-11)
Experience
Soc Design Engineer
Aug 2022 — Present · Bengaluru, IN
Education
Manipal Institute of Technology,ManipalUniversity : Manipal University
Master of Technology in Microelectronics, Vlsi
Visvesvaraya Technological University
Bachelor of Engineering, Electrical and Electronics
Skills
- Lvs
- Cadence
- Vlsi
- Analog
- Fresher
- Perl
- Physical Design
- Verilog
- Mems
- Drc
- Asic
- Matlab
- Microelectronics
- Very-Large-Scale Integration (Vlsi)
- Dft
- Testing
- Physical Verification
- Mixed Signal
- Cadence Virtuoso
- Semiconductors
- Systemverilog
- Electronics
- Sensors
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