Rahul Shekhar
Ex-Infocian | Actalent | MS EE | University of Southern California | Actively looking for internship/full-time opportunities
- Role
- Asic Design Engineer at Actalent
- Location
- Los Angeles, CA, US
- LinkedIn followers
- 500 followers
About Rahul Shekhar
I graduated from the University of Southern California in May 2025, specializing in…
Experience
Asic Design Engineer
Jan 2025 — Present · US
Architected a 7nm ASIC for a high-speed networking chip, integrating AXI4 interfaces and optimizing RTL design, achieving 15% power reduction through UPF-based low-power techniques.• Implemented DFT strategies including scan insertion and MBIST, improving fault coverage to 98% for 1M+ gates using TetraMAX and Synopsys TestMAX.• Performed synthesis and PnR with Cadence Innovus, meeting timing constraints with <3% setup margin and reducing chip area by 10%via optimized floorplanning.• Developed UVM testbenches for functional verification, achieving 95% code coverage and reducing verification cycle time by 25% with randomized test cases.• Collaborated with cross-functional teams to integrate IP blocks, ensuring CDC compliance and reducing design iterations by 20%
Education
University of Southern California
Master's degree, Electrical and Electronics Engineering
Maharashtra Institute of Technology
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
2015 — 2019
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