Rahul Sahu

About Rahul Sahu

Senior engineering leader with platform‑level ownership of memory and silicon IP execution across advanced technology nodes.I currently lead a multi‑geo engineering organization (India + Vietnam) at Qualcomm, responsible for end‑to‑end memory IP readiness spanning architecture, PPA optimization, design enablement, and cross‑program delivery.My role sits at the intersection of technology strategy, execution rigor, and people leadership — translating complex node‑level and cross‑org trade‑offs into predictable outcomes for large, multi‑stakeholder programs. I regularly operate in enterprise forums covering IP strategy, design‑process interlocks, and platform risk mitigation, with accountability for execution cadence and delivery predictability.I specialize in platform and horizontal capability ownership, scaling distributed engineering organizations, advanced‑node execution, and building senior technical leadership with sustainable succession.Inventor on 41 granted US patents, with additional patent applications and disclosures in progress.My career focus is on platform‑level leadership roles where I can own a horizontal capability and scale impact across regions and programs.

Experience

1. Director of Engineering

   Qualcomm

   Nov 2021 — Present · Bengaluru, IN

   Lead platform execution for the SRAM custom and compiler memory portfolio across multiple technology nodes, with accountability for PPA and schedule commitments.Own cross‑functional alignment across memory IP, process, verification, and SoC teams; drive trade‑off decisions for memory selection and adoption across programs.Manage and grow senior engineering teams across India and Vietnam, building technical leadership depth, succession, and sustainable execution models.Drive silicon bring‑up, debug, and yield recovery strategies, partnering with stakeholders through failure isolation, corrective actions, and stabilization.Lead memory test‑chip strategy and planning to validate new‑node readiness and de‑risk platform schedules.

Education

• Indian Institute of Technology, Delhi

  M.Tech

  2004 — 2006

• BIET Jhansi

  B.Tech, Electronics & Instrumentation

  1999 — 2003

Skills

• Debugging
• Low-Power Design
• Rtl Design
• Application-Specific Integrated Circuits (Asic)
• Eda
• Very-Large-Scale Integration (Vlsi)
• Cmos
• Integrated Circuits (Ic)
• Vhdl
• Simulations
• Asic
• Ic
• Soc
• Circuit Design
• System on a Chip (Soc)
• Sram
• 2
• Vlsi