Rahul Prakash Joshi

About Rahul Prakash Joshi

Architecture definition, Micro-architecture design.• Worked on variety of ASIC IP and SOC development projects. Handling complete development cycle RTL coding, Lint, CDC check, Synthesis, Timing closure.• FPGA based systems design, synthesis-PAR-Timing closure, board validation and ASIC prototyping.• Good experience of implementing complex algorithms in RTL- Video/Imaging: Canny Edge Detection, RAW (Bayer-RGB, Red-Clear) image Demosaicing with gradient based bi-linear interpolation, Contrast Enhancement by Histogram Equalization (with fixed point divider), Streaming Video multi-zone Histogram and Statistics computation per color component, Gamma correction with Piece-wise Linear approach, Image Scaler with Lanczos Filter- DSP: FFT radix-2 DIF/DIT butterfly algorithm - Compression: LZ77 (Lempel-Ziv) and Huffman-Tree Encoder for lossless data compression (GZIP)- Networking: Weighted Random Early Detection (WRED), Two Rate Three Color Marking (trTCM).• Good experience of implementing Arithmetic blocks- 754 standard Floating-Point Adder, Subtractor, Multiplier- Integer Adders (Ripple, Carry Look Ahead, Linear Carry Select), Signed Integer Multiplier- CORDIC - Polynomial evaluation accelerator for Direct-Substitution, Estrin and Horner methods, Defined RZC method (Filed Patent).• Experience of working on many industry-standard protocols like PCIe, CXL, RS-232, SPI, I2C, AXI, AHB etc.• Revenue responsibility. Pre-sales activities like project estimation, proposal creation/presentation. Project planning and execution including scheduling, resource allocation, task distribution, monitoring/mitigating schedule- & -effort variance and handling customer interactions.(with eInfochips).• Built and established Front-end Design Team (~25 design engineers) exhibiting strong leadership and managerial skills.(with eInfochips).

Experience

1. Principal Ip Architect (R & d)

   Renesas Electronics

   May 2025 — Present

   AI hardware accelerator# AI SOC

Education

• Pune Institute of Computer Technology

  Post Graduate Diploma in VLSI Design Tools and Techniques

  2001 — 2001

• M. S. Ramaiah School Of Advanced Studies (MSRSAS)

  Advanced Certification in Embedded Systems Design

  2003 — 2003

• Bharati Vidyapeeth

  B.E., Electrical

  1996 — 2000

• BITS Pilani Work Integrated Learning Programmes

  Master of Technology - MTech, Microelectronics

Skills

• Static Timing Analysis
• Spi
• Soc
• Altera
• Hardware Architecture
• Functional Verification
• Logic Analyzer
• Rtl Coding
• Logic Synthesis
• Fpga
• Asic
• Application-Specific Integrated Circuits (Asic)
• Rtl Design
• Ethernet
• Modelsim
• System on a Chip (Soc)
• Verilog
• Very-Large-Scale Integration (Vlsi)
• Vhdl
• Debugging
• Vlsi
• Field-Programmable Gate Arrays (Fpga)
• I2c
• Digital Signal Processors