Rahul Pippiri
ASIC RTL Design Engineer
- Role
- Asic Rtl Design Engineer at Micron Technology
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Rahul Pippiri
knowledge on CXL(compute express link) protocol.• Expertise in RTL design, simulation, and FPGA/CPLD design flow and verification.• Expertise in ADC and DAC peripherals driver level interface with FPGA.• Expertise in CDC & FPGA to FPGA communication protocol establishment.• Basic technical knowledge on PL to PS communication and vice versa.*Hands-on experience on quartus tools, agilex devices and CXL design• Hands-on experience, on Xilinx devices, Xilinx tools, and high-speed IP cores.• Development of test plan, test bench setup, and test environment.• Hardware board bring-up and debugging.• Expertise in Xilinx Primitives utilization.
Experience
Asic Rtl Design Engineer
Jul 2024 — Present
Education
State Board of Technical Education and Training (SBTET), Andhra Pradesh
Diploma, electronic and communications engineering
2010 — 2013
Centre for Development of Advanced Computing (C-DAC)
PG Diploma, Diploma in Electronic Product Design
2016 — 2017
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