Rahul Kumar
Senior Analog design Engineer at Intel Corporation || M.Tech IIITD
- Role
- Senior Analog Design Engineer at Intel
- Location
- New Delhi, DL, IN
- LinkedIn followers
- 500 followers
About Rahul Kumar
Analog Engineer at Intel with 4+ years of experience in IO circuit design, specializing in transistor-level development of 1.8V/1.2V/1V custom IO IPs across Intel and TSMC technology nodes. Proficient in the complete custom IO design flow, including specification definition, schematic/layout design, RTL vs schematic checks, ESD simulations, reliability analysis (EOS, EMIR, HV, ageing), and post-silicon debugging-Experienced in SoC-level integration and passionate about driving innovation while continuing to advance technically- Holder of an Intel-approved patent for a Decision Feedback Mechanism enabling 500mV overshoot/undershoot tolerance in thick-gate 1.8V IO designs- Published two research paper in well known conferences:1. Retention problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI, published in 2022, 35th International Conference on VLSI Design (VLSID).2. Design and benchmark of Iso stable high density 4T SRAM cells for 64MB arrays in 65 nm LSTP, published in 2020 17th India Council International Conference(INDICON).
Experience
Senior Analog Design Engineer
May 2025 — Present
Education
Ramakrishna mission school
Class 10
North Eastern Regional Institute of Science and Technology (NERIST)
Bachelor of Technology - BTech
2014 — 2018
Indraprastha Institute of Information Technology, Delhi
Master of Technology - MTech, VLSI and Embedded System
2019 — 2021
Oxford Public School Ranchi
Class 12
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