Rahul Dev

About Rahul Dev

13+ years of experience in DFT implementation and validation on complex IPs• Chip-level DFT insertion with, MBIST & JTAG techniques, and handling Analog Macros• post silicon DFT bring-up and debug experience • Defining the test mode strategy at IP level for clocking and power in test mode• Interfacing with Chip Top team to understand the DFT requirements• Test clock planning and optimization at IP level• Low power DFT implementation and cost optimization with Scan/LBIST• Good experience in ATPG, DRC analysis and coverage improvement• Scan, EDT and LBIST Insertion, ON chip clocking• RTL DFT checks using Spyglass• ATPG verification• Memory BIST implementation with built in self repair• Good exposure in Logical Equivalence Checking using Cadence Conformal LEC• Good exposure in generating functional ECO scripts manually and using Cadence Conformal LEC ECO tool• Exposure to Synthesis at block level• Exposure to Static timing analysis concepts

Experience

1. Soc Design Engineer

   Intel

   Jan 2021 — Present · IN

Education

• Visvesvaraya Technological University

  Bachelor of Engineering, Electronics and Communications

  1999 — 2003

• Kendriya Vidyalaya

  12th

• Vedant, Semiconductor Complex limited, Chandigarh

  Post graduate diploma, VLSI

  2003 — 2004

Skills

• Soc
• Cadence
• Modelsim
• Atpg
• Lec
• Logic Synthesis
• Vlsi
• Perl
• Eda
• Rtl Coding
• Debugging
• Integrated Circuit Design
• Drc
• Rtl Design
• Rtl
• Fpga
• Asic
• Bist
• Vhdl
• Spyglass
• Timing Closure
• Static Timing Analysis
• Verilog
• Dft
• Tcl