Rahul Changder

About Rahul Changder

Experienced Digital design and verification engineer with strong research background. Responsible for Micro-architecture design, RTL implementation, Spyglass LINT, CDC, RDC runs, and Cadence Synthesis runs, timing constraint, STA report analysis, ECO. LEC runs. Experienced in FPGA prototyping for Xilinx Kintex and Virtex Ultrascale devices. Primarily worked on memory modelling, IP generation, timing closure, bit stream generation and verification and debugging issues on the FPGA board. Proficient in Perl, Python and TCL based scripting and created multiple scripts for automating LINT, Synthesis and FPGA runs and report generation. Familiar with Cache, Flash and One Time Programmable (OTP) memories. Worked on UVM based verification, coverage analysis, and SV based assertions demonstrating excellent debugging and analytical capabilities. Designed, fabricated and characterized multiple MicroElectroMechanical System (MEMS) devices and publicized the results in publication. Possess strong leadership qualities along with vast experience in guidance and mentoring.

Experience

1. Asic Rtl Design Engineer

   Google

   Oct 2022 — Present

Education

• Indian Institute of Technology, Madras

  Master of Science (MS), Microelectronics and MEMS

  2017

Skills

• Comsol
• Microsoft Office
• Mathematica
• Microsoft Excel
• Powerpoint
• Coventorware
• Leadership
• Project Management
• Rf Mems
• Verilog
• Research
• Matlab
• Microsoft Word