Rahul Chandran
Fullchip Design Verification
- Role
- Silicon Design Verification at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Rahul Chandran
An expert in front-end verification with over 6 years of experience focused on IP level verification. Experienced in architecting & implementing Oops based constrained random test benches in system verilog for verifying complex designs. Experienced in starting projects from test plan and leading towards delivery. Experienced in training & managing resources in multiple projects.Very knowledgeable in industry standard protocols like PCie,OCP,AXI etc. & Methodologies like OVM & UVM.
Experience
Silicon Design Verification
Mar 2022 — Present · IN
Education
Cochin University of Science and Technology
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
2000 — 2004
Skills
- Digital Signal Processors
- Soc
- Systemverilog
- Rtl Design
- Arm
- Uvm
- Functional Verification
- Debugging
- C
- Vlsi
- Axi
- Amba Ahb
- Asic
- Pcie
- Verilog
- Open Verification Methodology
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