Rahul Bhati
Validation and Verification
- Role
- Test and Validation Engineer at 新思科技股份有限公司
- Location
- Faridabad, HR, IN
- LinkedIn followers
- 500 followers
About Rahul Bhati
HDL - Verilog HVL - System VerilogMethodology - UVM,OVMProtocol - UART,I2CTools - Questa sim,Modelsim,VCSScripting - LinuxLanguages - C,C++Programming fundamentals - OOPS, Data structures, AlgorithmHave good understanding of verificationenvironments.
Experience
Test and Validation Engineer
Jun 2024 — Present · Hyderabad, IN
Functional spec review,defining validation test plan, RTL/Test case creation,checkers,test running, regression track, regression analysis•Triage and bug reporting for the new enhancements and developed features •Review and Co-ordination with R&D,PE to indentify customer used models required to be validated and work on open critical Jira\'s to meet the quality expectations on the users
Education
Jc Bose University of Science and Technology Ymca
Bachelor of Technology, Electronics and Instrumentation Control Engineering
2018 — 2022
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