Rahul Bharadwaj
IP / ASIC Verification
- Role
- Verification Manager at AIonSi
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
Manufacturing & ProductionView LinkedIn profile
About Rahul Bharadwaj
Experienced Engineer in IP & Sub-system Verification. Strong hands on experience in…
Experience
Verification Manager
Jul 2024 — Present · Lund, SE
Education
VEDANT, Semiconductor Complex Limited,Mohali,Chandigarh,Punjab, India
Advanced PG Diploma in VLSI Design, VLSI
2003 — 2004
St.Andrews High School
High School
1984 — 1996
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Microelectronics
Jawaharlal Nehru Technological University
Engineer’s Degree, Electronics & Communications Engineering
1999 — 2003
Skills
- C/C++, Systemverilog, Vmm,Uvm
- Soc
- Debugging
- Semiconductors
- Static Timing Analysis
- Functional Verification
- Perl
- Eda
- Asic
- Rtl Design
- Amba Ahb
- System on a Chip (Soc)
- Systemverilog
- Verilog
- Universal Verification Methodology (Uvm)
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