Rahul Agarwal
Advisory R&D Engineer at IBM | Ex-Synopsys | Ex-Intel | BITS-Pilani
- Role
- Advisory R & d Engineer at IBM
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Rahul Agarwal
Good understanding in all aspects of Physical Design involving synthesis, PnRand timing closure• Involved in multiple tape outs of design varying from 795Mhz to 3.2GHzfrequency• Worked on SubFC level PnR and timing closure containing 2 blocks• Experience in Low Power Designs with UPF 2.0• Worked on multiple technologies varying from 16nm to 3nm
Experience
Advisory R & d Engineer
Aug 2025 — Present · Bengaluru, IN
Education
Birla School ,Pilani
Student
2008 — 2013
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Microelectronics
B K Birla Institute of Engineering & Technology, Pilani
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
2013 — 2017
Birla Shishu Vihar,Pilani
Student
2001 — 2008
Skills
- Electronics
- Application-Specific Integrated Circuits (Asic)
- Physical Verification
- Rtl Design
- Design Rule Checking (Drc)
- Pnr
- Routing
- Linux
- Vlsi
- Python
- Rtl Verification
- Public Speaking
- Tcl
- Cmos
- Adobe Photoshop
- Clock Tree Synthesis
- Cadence Encounter
- Physical Design
- Perl
- Floorplanning
- Static Timing Analysis
- Very-Large-Scale Integration (Vlsi)
- Semiconductors
- Verilog
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