Ragini Upadhyay
Sr. Design Verification Engineer @ Google
- Role
- Senior Design Verification Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Senior Design Verification Engineer
May 2024 — Present · Bengaluru, IN
Education
Bal Niketan Sangh
Higher Secondary, Mathematics and Computer Science
2003 — 2010
Indian Institute Of Information Technology Allahabad
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
2010 — 2014
Skills
- C++
- Integrated Circuit Design
- Microprocessors
- System on a Chip (Soc)
- Verilog
- Perl
- Embedded Systems
- Microcontrollers
- Application-Specific Integrated Circuits (Asic)
- Keil
- Xilinx
- Systemverilog
- Universal Verification Methodology (Uvm)
- Microsoft Office
- Vlsi
- Fpga
- Circuit Design
- C
- Digital Signal Processors
- Matlab
- Digital Electronics
- Embedded C
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