Raghuveer Shivaraj

About Raghuveer Shivaraj

Passionate and Tenacious technical leader with 20 years of experience in semiconductor industry with focused 18+ years of production oriented experience in strategic planning and execution of Design for Test, silicon debug and ramp to production. In depth know-how advanced DFT techniques involving memory bist, boundary scan, test compression and expertise in test cost reduction techniques. Digital Design and SOC integration involving complex power domain, clocking and reset management.Career Vision : Pioneer and technology leadership to drive and manage Mixed Signal SOC design, DFT and Test Engineering. I love to be part of a multifaceted organization in a challenging position, which would enhance and challenge my Mixed Signal SOC design, DFT expertise, Test Engineering experience, hardware design skills, and my VLSI design flow & methodology know-how.Key Strengths: Test planning of complex SOCs with power management. Advanced Scan & ATPG for stuck-at faults and at-speed testing for delay defects in DSM technology, Memory Bist and Boundary Scan. In depth know-how and experience in test compression and expertise in test cost reduction techniques. Test and debug of mixed signal components like protocol and high speed transceivers, data converters. Strategic planning and execution of DFT and SOC integration to meet multi site testing.

Experience

1. Principal Dft Architect Manager Ai Ml Ip Soc Group

   Marvell Technology

   Jul 2018 — Present · Santa Clara, CA, US

   Being one of the initial members of the group I had the responsibilities of hiring, planning and managing the DFT team members for the group along with Technical Leadership.•Defined all the test interfaces and drove several design micro-architecture strategies involving Clock, Reset and Power with the RTL and PD teams to able to take the designs from Spec to Silicon and customer delivery.•Was responsible for defining and driving the Day0 Silicon Bring up and Debug plan for ATE and Functional Silicon validation teams. •Work with Ops engineering team to define product life cycle management with planning and providing solutions for device qual from Engineering Samples to ramp to mass production.•Currently involved in defining the JTAG and MBIST implementation flows in the Infrastructure Processor Group in Marvell. Also provided the DFT implementation for the ML design integrated as an IP in the IPBU group.

Education

• Center For Development of Advanced Computing (CDAC India)

  Diploma, VLSI design - Post Grad Level

  2000 — 2001

• Bangalore University

  Bachelor of Engineering (BE), Telecommunications

  1996 — 2000

Skills

• Integration
• Timing
• Digital Design
• Atpg
• Vhdl
• Digital Design and Soc Integration
• Hardware Architecture
• Perl
• Eda
• Boundary Scan
• Dft
• Asic
• Bist
• Debugging
• Semiconductors
• Mixed Signal
• Perl Scripting
• Test Planning
• Modeling
• Verilog
• Rtl Design
• Design for Test, Atpg, Memory Bist, Jtag
• Integrated Circuit Design
• Characterisation Test Planing
• Behavioral Modeling and Pm Modeling for Soc Integration Verification
• Synthesis , Timing Constraints and Analysis
• Test Vector Compression and Test Cost Reduction
• Testing
• Soc
• Formal Verification
• Jtag for Soc and Test Control
• Vlsi
• Jtag
• Power Management
• Constraints