Raghul Cj
IIITA’27 ECE | RTL Design | FPGA | STA | AXI | RISC-V | IIITA’27 | Finalist @ MeitY Digital Design Hackathon | Coordinator Eda Wing Tesla IIITA
- Role
- Coordinator Eda Wing at Tesla, Iiit Allahabad
- Location
- Erode, TN, IN
- LinkedIn followers
- 500 followers
About Raghul Cj
Aspiring Digital Design Engineer | RTL / FPGA / ASIC | Finalist @ MeitY Hackathon | student at Allahabad, specializing in RTL design and FPGA-based systems. I’ve built custom Verilog IPs for real-time image processing, UART, and FIFO modules, all verified through simulation and synthesis on hardware (PYNQ-Z2). My work focuses on performance, correctness, and system integration using AXI protocols.I’ve been a national finalist in a Ministry of Electronics (MeitY) hackathon and actively mentor peers through the EDA Club at I’m currently expanding into ASIC flows and SystemVerilog-based verification, targeting industry-ready proficiency. Looking for internship opportunities in RTL Design, ASIC, FPGA, or Digital Verification domains.
Experience
Coordinator Eda Wing
Sep 2025 — Present
Education
The bvb
CBSE 10th Boards
2009 — 2020
Indian Institute Of Information Technology Allahabad
Btech
2023 — 2027
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