Raghu Krishna

About Raghu Krishna

Being as an \"ASIC Design Verification Engineer\"​ I have worked on IP level and sub system level. Major area on G02UVM, UVM-RAL (Register Models) and Ethernet Parser. Developed UVC\'s and verified with different testcases. I am looking for Full-time position in the field of ASIC Design Verification Engineer/Consultant.Experience in VLSI Front End Design & SoC/IP level Verification.Good Understanding and Programming Skills in Verilog & System Verilog.Hands on Experience with EDA tools ( Mentor graphics-Questa and Modelsim, Aldec- Rivera pro, Cadence- IUS).Specialties: Verilog, SystemVerilog, System Verilog Assertions, UVM(Methodology)- experience in ASIC Front End Verification- Good understanding of the ASIC Verification Flow & Testbench architecture- Good knowledge on Fundamental of Digital Design Concepts- Worked on Protocol- AMBA,UMC- Worked on Ethernet parser verification- Worked on code coverage\'s: code,functional,assertion coverage- Worked on IP,Sub-system and SOC level verification- Excellent knowledge of Verilog/SV/SVA- Worked on development of Testbench using HVL/HDL- Worked on UVM-RAL Modelling.

Experience

1. Staff Engineer

   Analog Devices

   Nov 2021 — Present · Bengaluru, IN

Education

• Acharya Institute Of Technology

  Bachelor's degree

  2003 — 2003

• Nagarjuna College Of Engineering and Technology

  Master's degree

  2010 — 2012

Skills

• Networking
• Matlab
• Rf
• Vhdl, Verilog Programming, Module Designing
• Wireless
• Very-Large-Scale Integration (Vlsi)
• Signal Processing
• Universal Verification Methodology
• Universal Verification Methodology (Uvm)
• Application-Specific Integrated Circuits (Asic)
• Lte
• Soc
• C
• Vlsi
• Asic
• Uvm-Ral
• Vhdl
• Simulations
• Modelsim
• Systemverilog
• Verilog
• Testing
• Powerpoint
• Telecommunications
• Embedded Systems
• Wireless Technologies
• Electronics
• System Verilog
• System on a Chip (Soc)