Raghu Bm
Intel - Standard cell / Custom digital circuit design engineer
- Role
- Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Raghu Bm
Standard Cells Design - 7nm, 5nm, 3nm PPA analysis and optimization.
Experience
Design Engineer
Jan 2016 — Present · Bengaluru, IN
Education
Birla Institute of Technology and Science, Pilani
Master’s Degree
2014 — 2016
Vemana Institute Of Technology
Bachelor’s Degree
Skills
- Verilog
- C
- Static Timing Analysis
- Vhdl
- Rtl Development
- Logic Synthesis
- Dft
- Perl
- Cadence Virtuoso
- Digital Circuit Design
- Modelsim
- Physical Design
- Integrated Circuit Design
- Analog Circuit Design
- System Verilog
- Eldo Spice
- Assembly Language
- Systemverilog
- Perl Automation
- Rtl Design
- Synopsys Hspice
- Open Verification Methodology
- Cadence Encounter
- Very-Large-Scale Integration (Vlsi)
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