Raghavendra Nadiger
Silicon CAD Engineer - Google
- Role
- Silicon Cad Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Raghavendra Nadiger
An enthusiastic VLSI Design automation engineer with a demonstrated history of working in the semiconductors industry both in FPGA and ASIC worlds. Skilled in- Design conceptualization- Electronic design flow automation- RTL integration- GUI development- IP-XACT AXI4 based Plug and Play IP development- DDR and NoC feature verification- IP packaging- RTL to PD hand-off- Release flow checks- CI/CD for tool deployment and flow automation- Static checks(Lint, CDC)- Memory Selection Methodology
Experience
Silicon Cad Engineer
Sep 2021 — Present · Bengaluru, IN
Own and lead the setup for subsystem flows qualification from scratch through Google’s in builtcontinuous integration tool similar to that of jenkins- Responsible for Lint flow development, tool version migration, flow documentation,deployment, profiling, debugging tool + flow issues, a single point of contact for the entire org forall issues related to Lint- Contributor to methodology & flow development of IP Versioning audit- Own Frontend RTL, UPF, SDC, IPXACT, Lint & CDC collateral Packaging, RTL Release flow for RTL2SOC, RTL2PD- Multi configuration IP qualification flow development and dashboarding for better tracking of IP deliveries
Education
Manipal School of Information Sciences
Master of Engineering (M.Eng.), VLSI Design
2015 — 2017
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