Raghavendra Kijanar
ASIC Verification Engineer
- Role
- Pre Silicon Verification Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Raghavendra Kijanar
Experienced Design Verification Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, C (Programming Language), Verilog, and Microsoft Office. Strong engineering professional graduated from M.S. Ramaiah Institute Of Technology.
Experience
Pre Silicon Verification Engineer
Sep 2022 — Present · Bengaluru, IN
Education
N M A M Institute of Technology, NITTE
Bachelor of Engineering - BE
2012 — 2015
Ramaiah Institute Of Technology
Master of Technology - MTech
2015 — 2017
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