Raghavendra B Nagashrith

About Raghavendra B Nagashrith

9 years of experience in VLSI Layout Design and Passionate towards layout design. As an engineer to make the best use of my skills, knowledge and contribute effectively to the organisation Skills-1.Layout design(Standard cells) experience in various technologies - 180nm,90nm,45nm,28nm,FinFet(16nm,4nm,5nm,3nm,2nm)2. Worked on different Standard cell libraries of different architectures in various technologies of Samsung, TSMC, Intel foundries3. Worked on Standard cell Architecture analysis 4. Basic concepts of Analog layout5.Verification checks such as DRC,LVS,ERC,DFM6.Cadence SKILL scripting, Calibre SVRF coding7.Handling of Physical views generation of LEF, MILKYWAY, NDM8. Handled different libraries in multiple technologies.9. Layout PPA optimisation for various technologies Scripting-1. Cadence SKILL2. Calibre SVRFEDA Tools- 1. Cadence Virtuoso2. Calibre 3. Abstract4. ICV5. CalibredrvInterests-1. Layout Design(Analog and Digital)2. VLSI Physical design.3. Scripting

Experience

1. Senior Layout Designer

   Intel

   Jun 2022 — Present · Bengaluru, IN

   Custom Standard cell layout development in TSMC(2nm,3nm), INTEL technologies2. Layout development of Custom Flops,Level shifters, Multi-bit Flops, Global Clock Cells3.Calibre SVRF Coding for the development of Boundary checks in TSMC(2nm,3nm) technologies 4.LEF, NDM Generation

Education

• Manipal Institute of Technology(MIT)

  Master of Technology (MTech), DIGITAL ELECTRONICS AND ADVANCED COMMUNICATION

  2013 — 2015

• Sri Bhagawan Mahaveer Jain College

  Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering

  2008 — 2012

Skills

• Cadence Virtuoso
• Digital Circuit Design
• Vlsi
• Physical Design
• Spice
• Integrated Circuit Design
• Pvs
• Asic
• Parasitic Extraction
• Verilog
• Semiconductors
• Lvs
• Electronics
• Simulations
• Eda
• Analog
• Standard Cell
• Ic Layout
• Eldo
• C++
• Calibre
• Drc
• Cmos
• Layout Design