Raghava Chethan Manipatruni

Staff Engineer-analog & Mixed Signal Design @Synopsys Inc

Hyderabad, TG, IN
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WORK HISTORY

Mar 2024 — Present

Staff Engineer-analog & Mixed Signal Design @Synopsys Inc

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Hyderabad, IN

EDUCATION

1998 — 2008

Kendriya Vidyalaya

CLASS 10

2010 — 2015

GITAM Deemed University

Integrated Dual Degree ( B.Tech + M.Tech ), B.Tech in Electronics and Communication Engineering & M.Tech In VLSI Design

2008 — 2010

NARAYANA JUNIOR COLLEGE

INTERMEDIATE, M.P.C

ABOUT RAGHAVA CHETHAN MANIPATRUNI

Experienced lead Analog mixed signal IP Design Engineer with a demonstrated history of working in the industry with special focus on high speed SerDes, especially PLL, Oscillators, CDR and power circuits like BGR, Regulator and bias. Worked on AMS designs like Resistance calibration, PLL Calibration, Rx Timing Recivery DSP models, phase interpolators and complete chip clock scheme Familiar with PCIE,SATA, HSSTP, different Ethernet protocols ( 10Gbase-KR) Experience in hardening of different high speed digital PLLs. Worked on Silicon bring up and debug of high speed SerDes and also worked on post processing. Worked on various process modes from 6nm to 65nm.Also a Strong engineering professional with a Distinction degree.

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Raghava Chethan Manipatruni — Staff Engineer-analog & Mixed Signal Design at Synopsys Inc in Hyderabad, TG, IN | Unifers